1. Field of the Invention
The present invention relates to an integrated circuit having multiple conductor levels for interconnection of circuitry.
2. Description of the Prior Art
Integrated circuits (IC's) typically utilize multiple levels of conductors for distributing power supply voltages, as well as operational signals, between various portions of the IC. The conductors are most typically metal in the case of power supply distribution, usually aluminum, tungsten, titanium or gold, with still others (e.g., copper) being possible. These provide high conductivity and hence low voltage drop as power supply current flows. In the case of signal conductors, an even wider range of materials is often used, including doped polysilicon, metal silicides and metal nitrides in addition to the metals noted above. Conductors are formed by lithographically patterning a given level of conductive material, to form conductive lines as viewed from above an IC substrate. The conductor levels are separated from one another by dielectric layers for electrical insulation. The dielectric is often a glass (e.g., silicon dioxide including phosphorus and/or boron) at the lowest level (i.e., the level nearest the semiconductor substrate). The use of silicon dioxide is typical as an interlevel dielectric between the higher conductor levels (i.e., the levels overlying the lower conductor levels). The conductors may communicate by means of openings in the dielectric layers, referred to as "vias", with other conductor levels. The conductors also may communicate to doped device regions in the semiconductor substrate by means of openings in the lowest dielectric level, referred to as "contact windows".
The art of laying out the conductors has been developed to a high degree in the integrated circuit art. The factors that affect layout include the desire for a high density of interconnections while minimizing the length of interconnects. It is apparent that the more levels of conductors are available in a given IC technology, the more freedom is possible for laying out the conductors. In one typical 0.9 micron CMOS logic technology, one polycide (doped polysilicon/silicide) level and two aluminum levels are used. The bottom metal level is referred to as "metal 1", whereas the top metal level is referred to as "metal 2". However, as IC geometries shrink to the 0.5 micron level, the number of metal conductors levels has often been increased to three or more.
One typical form of conductor layout is illustrated in FIG. 1, wherein the metal conductors 109-115 lie in wiring channels between various ones of the functional circuit blocks 101-108. The metal conductors may extend from the wiring channels into the circuit blocks as indicated. Usually only the metal conductors are located within the wiring channels, while within a given circuit block, both the metal conductors and the polysilicon/silicide conductors are used. The circuit blocks shown are typical for use in a digital signal processor (DSP), which is chosen to be illustrative of the prior art. For example, a DSP typically includes a central processing unit (CPU) 101 that includes arithmetic address unit (AAU) 102, a sequence control unit (SCU) 103, a digital arithmetic unit (DAU) 104, and sometimes also a bit manipulation unit (BMU) 105. The CPU 101 communicates with a random access memory (RAM) 106, a read-only memory (ROM) 107, and an input/output (IO) unit 108. When implemented in two-metal level technology, the long conductors in the wiring channels (e.g., 109, 110, 111, 112, 113, 114, 115) are formed in metal 2. The short stubs that feed into the modules (e.g., 116, 117, 118, 119) are formed in metal 1, and connected to the associated metal 2 conductors with vias.
Some of the conductors (109, 111) turn the corner around a block (106) to change from a horizontal to a vertical conductor, while avoiding crossing over of another conductor. However, some conductors cross over other conductors. For example, conductor 110 connects to conductor 113 by means of a cross-under portion 120 that is formed in metal 1, and connected by means of vias 121 and 122. This allows conductor 112 to cross-over without connection to conductor 110. Still another example is cross-under conductor 123. Note that the boundaries of the circuit blocks are shown as dotted lines. These boundaries may include power and ground (V.sub.DD and V.sub.SS) conductors, typically in metal 2. For example, in one case V.sub.DD was used on two sides of a circuit block, whereas V.sub.SS was used on the other two sides. In another case, a V.sub.DD encompassed an entire circuit block, whereas V.sub.SS encompassed another circuit block. The stubs that feed V.sub.DD and/or V.sub.SS into the modules are then typically implemented in metal 2. At these places the interconnect wires cross under in metal 1.
The use of three (or more) metal levels is also known in the integrated circuit art. In one case, the power and ground conductors are formed in the wiring channels parallel to the signal conductors. These power supply conductors then turn into the circuit blocks (i.e., at fight angles to the wiring channels), and are jumpered down by vias to the metal 2 and metal 1 conductors as required inside the circuit blocks.